1. Field of the Invention
The present invention relates to semiconductor devices and a method for producing the semiconductor devices, and more particularly, to a semiconductor device comprising at least one bipolar transistor and an isolating region, e.g. a so-called VIP (V-groove isolation polycrystalline silicon backfill) isolating layer for isolating the bipolar transistor from other elements.
2. Description of the Prior Art
A known combination of a bipolar transistor with a VIP isolating layer for semiconductor devices, e.g. IC and LSI, is illustrated in FIG. 1. In FIG. 1, the bipolar transistor (in this case, this transistor is an npn type bipolar transistor) comprises an n-type collector region 1, a p-type base region 2 and an n-type emitter region 3 which are formed in an n-type epitaxial layer 4 grown on a p-type semiconductor substrate 5. The transistor, moreover, has an n.sup.+ -type buried layer 6 and an n.sup.+ -type region 7 for electrical contact. The bipolar transistor is surrounded by the VIP isolating layer so that the bipolar transistor is isolated from other elements of the semiconductor device. The VIP isolating layer comprises an insulator layer 8 formed on a side surface of a V-groove 9, a polycrystalline silicon layer 10 filling the inside space of the V-shaped insulator layer 8 and a relatively thick insulating layer 11. The bottom peak of the V-groove 9 enters the semiconductor substrate 5 through the epitaxial layer 4. It is preferable to form a p.sup.+ -type buried layer 12, which surrounds the V-groove 9 and serves as a channel stopper, in the upper portion of the semiconductor substrate 5.
The above-mentioned npn type bipolar transistor with the VIP isolating layer is produced in the following manner. The starting material is the p-type semiconductor substrate 5, e.g. a silicon single-crystal wafer. The n.sup.+ -type buried layer 6 is selectively formed in the upper portion of the semiconductor substrate 5 by a thermal diffusion process or an ion implantation process. The p.sup.+ -type buried layer 12 is selectively formed in the upper portion of the semiconductor substrate 5 so as to surround the n.sup.+ -type buried layer 6 by a thermal diffusion or an ion implantation process. In a case where the ion implantation process is carried out, the semiconductor substrate 5 with the buried layers 6 and 12 is annealed. Then, the n-type semiconductor (e.g. silicon) epitaxial layer 4 is formed on the semiconductor substrate 5 by a conventional epitaxial growth technique.
An insulating layer 13 (e.g. a silicon dioxide layer) is formed on the epitaxial layer 4 by a thermal oxidation process. In FIG. 1, the reference numeral 13 indicates portions of the insulating layer. An oxidation masking layer (e.g. a silicon nitride layer, not shown) is formed on the insulating layer 13 by a chemical vapor deposition (CVD) process. Then, the oxidation masking layer and the insulating layer 13 are selectively etched by a conventional photolithography technique to form a predetermined opening (not shown). Using the oxidation masking layer and insulating layer 13 as a mask, the V-groove 9 is formed in both the epitaxial layer 4 and the semiconductor substrate 5 by anisotropically etching them with a suitable etchant. The bottom peak of the V-groove 9 enters the semiconductor substrate 5 through the p.sup.+ -type buried layer 12, as illustrated in FIG. 1.
The insulator layer 8 (e.g. a silicon dioxide layer) is formed on the surface of the V-groove 9 by a thermal oxidation process. A polycrystalline silicon layer is formed on the surfaces of the oxidation masking layer and the insulator layer 8 and, then, is polished to remove all except the portion 10 of it which remains within the V-groove. The remaining polycrystalline silicon layer 10 is thermally oxidized to form a relatively thick insulating layer 11 (i.e. a silicon dioxide layer), as illustrated in FIG. 1.
The P-type base region 2, a portion of which comes into contact with the insulator layer 8, is formed in the n-type collector region 1 of the epitaxial layer 4 by an ion implantation process. The n.sup.+ -type emitter region 3, a portion of which comes into contact with the insulator layer 8, is formed in the base region 2 and, simultaneously, the n.sup.+ -type region 7 for electrical contact is formed in the collector region 1 by an ion implantation process. It should be noted that it is possible to form the regions 2 and 3 by a thermal diffusion process instead of the ion implatation process. After the ion implantation process, and annealing treatment for the base region 2 and emitter region 3 is carried out. The insulating layer, except for the portion 13, is removed by a photolithography technique to expose the surface portions of the epitaxial layer 4. Finally, metal (e.g. aluminum) electrodes 14, 15 and 16 are formed so as to come into contact with the exposed surface portions of the epitaxial layer 4, as illustrated in FIG. 1, by a suitable techniquie for forming patterned metal layers.
The above-mentioned bipolar transistor with the VIP isolating layer has the advantage that dimensions of the bipolar transistor are small and, accordingly, the degree of integration of an IC or LSI is high, since the portions of the base region and the emitter region come into contact with the VIP isolating layer, i.e. the insulator layer in the V-groove. However, as shown in FIG. 2a, a so-called bird's beak 17 of silicon dioxide is inevitably formed at a joining portion of the insulating layer 13 and the relatively thick insulating layer 11, when the thick insulating layer 11 is formed by a thermal oxidation process.
The ion implantation process for forming the base region 2 (FIG. 2a) and the emitter region 3 (FIG. 2b) will now be explained in more detail. Using a patterned photo resist 18 as a mask, p-type impurities (e.g. boron, aluminum or gallium) are introduced into the epitaxial layer 4 by ion implantation to form the base region 2. In this case, since the impurities are introduced at various depths, in accordance with a profile of the bird's beak 17, the bottom face of a portion of the base region 2 located under the bird's beak 17 gradually becomes tapered upward, as illustrated in FIG. 2a. The photo resist 18 is removed and then the insulating layer 13 is etched to form an opening 19 (FIG. 2b) by photolithography. When the etching is performed, the etchant (e.g. HF solution) etches not only the insulating layer 13 but, also, the bird's beak 17 and a side portion of the thick insulating layer 11, as illustrated in FIG. 2b. N-type impurities (e.g. phosphorus, arsenic or antimony) are introduced through the opening 19 into the base region 2 by ion implantation to form the emitter region 3. The bottom face of the emitter region 3 is flat, so that the end of the tapered portion of the base region 2 either comes into contact with the emitter region 3 near the insulator layer 8 within the V-groove 9, as illustrated in FIG. 2b, or approaches the emitter region 3, but does not quit contact it (in this case, not shown).
If the bottom face of the base region 2 comes into contact with that of the emitter region 3, a short-circuit between the collector and the emitter will occur. Furthermore, as the bottom face of the base region 2 approches that of the emitter region 3, the breakdown voltage between the collector and the emitter decreases. In a case where the above-mentioned bipolar transistors are used in a high speed IC or LSI, those transitors have a thinner base thickness than an ordinary bipolar transistor, so that disadvantages, such as the above-mentioned short-circuit and decrease of the breakdown voltage, occur frequently in the bipolar transistors in the high speed IC or LSI.